Read circuit for non-volatile memories

ABSTRACT

A read circuit for non-volatile memories having an array section, with a corresponding bitline, and a reference section, with a corresponding reference bitline. A differential amplifier for comparing voltage signals obtained by current/voltage conversion of a current signal of an array cell and of a reference current signal is connected to the respective bit lines. A cascode transistor for each one of the array and reference sections, each driven by a NOR logic gate; a charge transistor for the bitline and a charge transistor for the reference bitline; column decoding transistors for the array section and for the reference section; the circuit further comprising an additional transistor which is connected between the NOR gate of the array side and a node for acquiring the array voltage sent to the differential amplifier, the additional transistor increasing the speed of the process for reading the bitline when the bitline is not charged.

TECHNICAL FIELD

The present invention relates to a read circuit for non-volatilememories. More particularly, the invention relates to a circuit forreading the state of the cells of a non-volatile memory, such as anEPROM, EEPROM and FLASH-EEPROM, which is known as sense amplifier, ofthe static type.

BACKGROUND OF THE INVENTION

It is known that in the latest generations of memories there has been areduction in power consumption and an increase in the capacity and sizeof memory arrays, which entail an increase in capacitive load both forthe wordlines and for the bitlines.

This situation can cause reading delays and reduce the performance ofthe memory if measures are not taken both technologically and in thedesign stage. For example, the delay due to the time constant (RC)associated with the wordline can be reduced by metal strapping, so as toreduce its resistance (since the capacitance of the wordline hasincreased).

The delay due to the increased capacitance of the bit line can insteadbe reduced by increasing the dimensions of the pass transistors of thecolumn decoder of the memory cells array and of the correspondingdriving circuits, or by boosting the driving signals of the passtransistors of the column decoder. These solutions, aimed at reducingthe resistance involved, have the drawback that the read circuit thusmodified occupies a considerable silicon area.

SUMMARY OF THE INVENTION

The aim of the present invention is to provide a read circuit fornon-volatile memories which provides an increase the speed of the memoryreading process.

Within the scope of this aim, an object of the present invention is toprovide a read circuit for non-volatile memories which allows to reducethe charge times of a bitline involved in a reading process.

Another object of the present invention is to provide a read circuit fornon-volatile memories in which the increase in the speed of the memoryreading process is achieved with a substantially negligible increase inoccupied silicon area.

Another object the present invention is to provide a read circuit fornon-volatile memories which is highly reliable, relatively easy tomanufacture and at competitive costs.

This aim, these objects and others which will become apparenthereinafter are achieved by a read circuit for non-volatile memorieshaving an array section, with a corresponding bitline, and a referencesection, with a corresponding reference bitline. A differentialamplifier for comparing voltage signals obtained by current/voltageconversion of a current signal of an array cell and of a referencecurrent signal is connected to the bitline and reference bitline. Acascode transistor is provided for the array and the reference section,driven by a NOR logic gate. There is a charge transistor for the bitlineand a charge transistor for the reference bitline. Column decodingtransistors are provided for the array section and for the referencesection. An additional transistor is connected between said NOR gate ofthe array side and a node for acquiring said array voltage sent to saiddifferential amplifier, the additional transistor increases the speed ofreading the bitline when the bitline is not charged.

BRIEF DESCRIPTION OF THE DRAWINGS

Further characteristics and advantages of the present invention willbecome apparent from the following detailed description of a preferred,but not exclusive embodiment, of the device according to the invention,illustrated only by way of non-limitative example in the accompanyingdrawings.

FIG. 1 is a circuit diagram of a conventional memory read circuit.

FIG. 2 is a circuit diagram of a memory read circuit according to thepresent invention.

FIGS. 3 shows charts which schematically illustrates the basic principleof the present invention.

FIGS. 4 and 5 are charts of a comparison of the behavior of conventionalread circuits and according to the present invention, respectively forreading a programmed memory cell and a virgin cell.

DETAILED DESCRIPTION OF THE INVENTION

With reference to the above figures, FIG. 1 shows a circuit for readingnon-volatile memories, i.e., a conventional static sense amplifier,generally designated by the reference numeral 1.

In this circuit, the currents of the array cell and of the referencecell (not shown) are compared by a differential amplifier (designated bythe reference numeral 2 in FIG. 1) by using current/voltage converterswith a ratio of 2 (the P-channel transistors 3, 4 and 5 have the samedimensions).

Feedback cascode circuits, constituted by transistors 6 and 7 in whichthe respective gate terminals are driven by respective logic gates, 8and 9, are connected to N-channel MOS transistors 10, 11 and 12, 13,respectively for the memory cell array side and for the reference side.

The transistors 10-13 are column selection transistors for the array ofmemory cells and for the array of reference cells, where BL is thebitline and BLREF is the reference bitline of the reference side. Thesefour transistors receive the column selection signals at their gateterminals.

The NOR-type gates 8 and 9 shown herein are slightly different from anormal NOR gate, which would be constituted by a pair of N-channel MOStransistors 14, 15 (for the gate 8) and 16, 17 (for the gate 9) whichare parallel-connected and by a pair of P-channel MOS transistors 18, 19(for the NOR gate 8) and 20, 21 (for the NOR gate 9) arranged in series,whereas in the NOR-type gates shown in FIG. 1 the gate terminals of thetransistors 19 and 21 are connected to the ground instead of beingconnected so as to receive in input the signal DATUM and the referencesignal DATUMREF. Of course, any acceptable logic gate, NAND, NOR, AND,etc. could be used for this inventive circuit based on the principlestaught herein.

The NOR gates 8 and 9 also receive in input, in addition to the signalsDATUM and DATUMREF applied to the gate terminals of the transistors 15and 16, a signal ENSAN applied to the gate terminals of the transistors14 and 17.

The differential amplifier 2 receives in input a pair of signals MATSand REFS, respectively from the array side and from the reference side,which are proportional to the currents of the array side and of thereference side, in order to compare them and emit a signal DIFFOUT whichpasses through a pair of cascade-connected inverters 22 and 23 toproduce the output signal OUTSA.

The conventional read circuit is completed by a pair of N-channel MOStransistors 24 and 25, one for the array side and one for the referenceside, which increase the speed of the precharging of the bitline BL andof the reference bitline BLREF.

Finally, additional P-channel MOS transistors 26 and 27 areparallel-connected to the transistors 3, 4 and 5 respectively andreceive, at their gate terminals, the signal ENSA for enabling the senseamplifier. In standby conditions, the enable signal ENSA is kept low, sothat the signals FBMAT and FBREF are low and the N-channel transistors6, 7, 24 and 25 are off while the differential amplifier is not powered.

In this situation, power consumption is nil. In the above condition,since the signal ENSA is low, the P-channel transistors 26 and 27 are onand bring the nodes MATS and REFS to a voltage which is equal to thepower supply Vcc.

Each one of the transistors 4 and 5 has dimensions which are equal tothose of the transistor 3, so that from a resistive point of view thearray side has a 2:1 ratio with respect to the reference side.

The cascode circuits (transistors 6 and 7) set the maximum voltage onthe array cells and on the reference cells, so as to avoid so-called"soft writing", uncouple the output nodes from the high-capacitancenodes due to the bitlines BL and BLREF and to the column selectors(transistors 10-13), and also provide a first level of amplification.

The circuit according to the invention is now described with referenceto FIG. 2, which shows that the difference with respect to the circuitshown in FIG. 1 is the presence of an additional P-channel MOStransistor 30 which is parallel-connected to the P-channel MOStransistor 19.

The gate terminal of the said P-channel MOS transistor 30 is connectedto the node designated by MATS and is therefore added to the NOR gate 8.

The usefulness of the transistor 30 is apparent in the step for readinga nonprogrammed memory cell, i.e., a memory cell which is in a state ofhigh threshold voltage (not shown in the figures) and belongs to anon-charged bitline.

The principle on which the addition of the transistor 30 is based is theone shown in FIG. 3. As shown in the top plot of FIG. 3, graphing inputvoltage over time, the charging of an RC circuit performed with a signalVin (voltage step) which is constant, designated by "a" in FIG. 3,produces an output signal Vout which has the behavior shown by the curve"a" in the bottom plot of FIG. 3.

However, if the input signal Vin had a slight overshooting, as shown bythe curve "b" in the top plot of FIG. 3, the output signal Vout wouldhave the behavior shown by the curve "b" in the bottom plot of FIG. 3,which is above curve "a" in the initial time step. In other words, theoutput for an input signal "b" reaches the final value sooner.

Accordingly, this concept is applied to the step for charging thebitline BL, which in practice constitutes the RC circuit, since theresistance R can be viewed as the resistance of line selectiontransistors 10 and 11, in addition to the resistance of the bitline BLitself, while the capacitance C can be viewed as the capacitance of thebitline BL.

The transistor 30 thus allows to achieve a slight overshoot on the nodeDATUM, which is common to the source terminal of the transistor 6 (whichconstitutes the cascode circuit) and accordingly allows to charge thebitline BL more quickly, but only if the bitline is not charged.

In this case, the gate terminal of the transistor 6, node designated byFBMAT, almost reaches the supply voltage Vcc and the transistor 24enters the triode region. The charge current is very high and thepotential of the node MATS drops below 1 volt; accordingly, the MOStransistor (of the P-channel type) is on and the operating point of theNOR gate 8 is raised.

The node FBMAT in fact reaches a higher peak value and this allows thenode DATUM to charge to a value higher than the one that occurs at theend of the charge transient, i.e., the sought overshooting occurs.

The invention thus includes a method sensing data comprising precharginga sense amplifier 2, selecting an array bit line, enabling a referencebit line, coupling the array bit line to a first input of the senseamplifier by 2 driving a first switching transistor into a conductionmode with an output signal of a first logic gate 8, coupling thereference bit line to a second input of the sense amplifier 2 by drivinga second switching transistor into a conducting mode with an output of asecond logic gate 9, and providing an additional current path via anadditional transistor 30 to the output signal of the first or secondlogic gate for increasing the speed of coupling the array bit line tothe input of the sense amplifier.

The charts of FIGS. 4 and 5 clarify the operation of the circuitaccording to the invention with respect to the conventional circuit.

In FIGS. 4 and 5, the various signals plotted are repeated for thecircuit of FIG. 1 and for the circuit of FIG. 2, i.e., for theconventional circuit and for the circuit according to the presentinvention, in order to provide a performance comparison which issignificant so as to point out the improvement to the reading processprovided by the circuit according to the present invention.

Accordingly, the signals related to the circuit of FIG. 1 are designatedby the reference numeral 1 followed by the name of the signal, while thesignals of the circuit of FIG. 2 are designated by the reference numeral2 followed by the name of the signal.

However, such signals are designated by the same reference signs inFIGS. 1 and 2 without adding identification numbers.

The chart of FIG. 4 shows that the bitline BL reaches, in this case, thefinal value more quickly than the conventional circuit of FIG. 1.

This leads to an earlier occurrence of the time when the signal MATScrosses the signal REFS and also of the time when the output of thedifferential amplifier switches.

It is thus evident that with the transistor 30 the reading process isfaster than in the case shown in FIG. 1.

The chart of FIG. 5 instead plots the case of reading a nonprogrammedcell (low threshold voltage state) which again belongs to a non-chargedbitline that must be charged initially.

In this case, the transistor 30 has no effect on the operating speed,which is of course higher than the preceding one (chart of FIG. 4).

Moreover, the transistor 30 does not influence the levels of the signalsin the steady state; this is why it does not intervene when reading abitline BL which has remained charged after a previous reading.

In practice it has been observed that the circuit for readingnon-volatile memories according to the invention fully achieves theintended aim and objects, since it allows faster reading of anon-charged bitline with a practically negligible silicon areaconsumption and without adverse effects on the other conditions in whichthe bitline may be.

Since the connection of the transistor 30 introduces a new feedback pathin the array side, to avoid instability problems it is desired for thedesigner to select appropriate dimensions for the transistor 30, andalso control the phase margin so as to always be in a stable condition.Such selections are well known and once the disclosure of this inventionis provided, can easily be done by one of skill in the art.

The circuit according to the present invention is particularly suitablefor reading high-density non-volatile memories with a low supplyvoltage.

The circuit for reading non-volatile memories thus conceived issusceptible of numerous modifications and variations, all of which arewithin the scope of the inventive concept; all the details may also bereplaced with other technically equivalent elements.

In practice, the materials employed, so long as they are compatible withthe specific use, as well as the dimensions, may be any according torequirements and to the state of the art.

Of course, the transistor 30 to provide the additional current pathcould instead be provided in reference bit line and operate on similarprinciples with respect to the reference bit line.

The disclosures in Italian Patent Application No. MI97A002458 from whichthis application claims priority are incorporated herein by reference.

What is claimed is:
 1. A read circuit for non-volatile memories,comprising:an array section, with a corresponding bitline, and areference section, with a corresponding reference bitline; adifferential amplifier for comparing voltage signals obtained bycurrent/voltage conversion of a respective current signal of an arraycell and of a reference current signal; a cascode transistor for eachone of said array and reference sections, each driven by a logic gate; acharge transistor for said bitline and a charge transistor for saidreference bitline; column decoding transistors for said array sectionand for said reference section; and an additional transistor which isconnected between said logic gate of the array section and a node foracquiring said array voltage signal sent to said differential amplifierfor comparison with the reference voltage converted current signal, saidadditional transistor increasing the speed of the process for readingsaid bitline when said bitline is not charged.
 2. The read circuit fornon-volatile memories according to claim 1 wherein said additionaltransistor is a P-channel MOS transistor.
 3. The read circuit accordingto claim 1 wherein said logic gates are NOR gates.
 4. The read circuitfor non-volatile memories according to claim 1 wherein each one of saidNOR gates is connected between a power supply line and ground andcomprises a pair of P-channel MOS transistors which are arranged inseries and are connected to a pair of N-channel MOS transistors whichare arranged in parallel, one of said P-channel MOS transistorsreceiving in input an inverted signal for enabling said referenceamplifier and one of said N-channel MOS transistors receiving in input areading datum signal, a gate terminal of the other one of said P-channelMOS transistors being connected to the ground.
 5. The read circuit fornon-volatile memories according to claim 4 wherein said additionaltransistor is parallel-connected to said P-channel MOS transistor, whosegate terminal is connected to the ground.
 6. The read circuit fornon-volatile memories according to claim 1 wherein said node foracquiring the voltage signal that is proportional to the array currentto which the gate terminal of said additional transistor is connected isarranged so that it is connected to a node for sending a voltage signalwhich is sent to the differential amplifier and is generated by at leastone of the current/voltage converter transistors.
 7. The circuitaccording to claim 1 wherein the additional transistor is disabled oncesensing is complete.
 8. A read circuit for a memory comprising:an arrayof memory cells; an array bit line coupled to memory cells in the array;a sense amplifier having a first input and a second input; a firstcoupling transistor coupled to the array bit line and to the first inputof the sense amplifier; a first logic gate having its output coupled todrive a control terminal of the first coupling transistor; a referencememory cell; a reference bit line coupled to the reference memory cell;a second coupling transistor coupled to the reference bit line and tothe second input of the sense amplifier; a second logic gate having itsoutput coupled to drive a control terminal of the second couplingtransistor; and an additional transistor having a control gate coupledto an input to the sense amplifier and providing an additional currentpath to the output of the first or second logic gate when the transistoris enabled.
 9. The circuit according to claim 8 wherein said additionaltransistor has its control gate coupled to the first input and providesan additional current path to the output of the first logic gate. 10.The circuit according to claim 8 wherein said additional transistor hasits control gate coupled to the second input and provides an additionalcurrent path to the output of the second logic gate.
 11. The circuitaccording to claim 8 wherein the logic gate is a NOR gate.
 12. Thecircuit according to claim 8 wherein the additional transistor isdisabled once sensing is complete.
 13. The circuit according to claim 8,further including pull-up transistors coupled to the inputs of saidsense amplifier.
 14. A method sensing data comprising:precharging asense amplifier; selecting an array bit line; enabling a reference bitline; coupling the array bit line to a first input of the senseamplifier by driving a first switching transistor into a conducting modewith an output signal of a first logic gate; coupling the reference bitline to a second input of the sense amplifier by driving a secondswitching transistor into a conducting mode with an output of a secondlogic gate; and providing an additional current path to the outputsignal of the first or second logic gate for increasing the speed ofcoupling the array bit line to the input of the sense amplifier.
 15. Themethod according to claim 14, further including:turning the firstswitching transistor off when the bit line reaches a logic one value.16. The method according to claim 14 wherein said first logic gate is aNOR gate.
 17. The method according to claim 14, further includingdisabling the additional current path after the sense amplifier hadcompleted the sensing of the selected array bit line.
 18. A read circuitfor non-volatile memories further comprising:an array section, with acorresponding bitline, and a reference section, with a correspondingreference bitline; a differential amplifier for comparing voltagesignals obtained by current/voltage conversion of a current signal of anarray cell and of a reference current signal; a cascade transistor foreach one of said array and reference sections, each driven by a logicgate; a charge transistor for said bitline and a charge transistor forsaid reference bitline; column decoding transistors for said arraysection and for said reference section; and an additional transistorwhich is connected between said logic gate of the array section and anode for acquiring said array voltage signal sent to said differentialamplifier for comparison with the reference voltage converted currentsignal, said additional transistor increasing the speed of the processfor reading said bitline when said bitline is not charged; andcurrent/voltage converter transistors arranged at said reference sectionand at said array section, said converter transistors being twice asmany as the converter transistors of said array section.
 19. The readcircuit for non-volatile memories according to claim 18 wherein saidadditional transistor is a P-channel MOS transistor.
 20. The readcircuit according to claim 19 wherein said logic gates are NOR gates.21. The read circuit for non-volatile memories according to claim 18wherein said node for acquiring the voltage signal that is proportionalto the array current to which the gate terminal of said additionaltransistor is connected is arranged so that it is connected to a nodefor sending a voltage signal which is sent to the differential amplifierand is generated by at least one of the current/voltage convertertransistors.
 22. The circuit according to claim 18 wherein theadditional transistor is disabled once sensing is complete.